技术“叠叠乐”，算力节节高！ - 科技资讯(世良情感网)

近日，在2025年IEEE国际固态电路会议（ISSCC 2025）上，英特尔分享了数项研究进展，涵盖协议级集成、集成电源和热管理、硅光集成等多个前沿技术领域。这是全球固态电路和系统芯片领域最重要的论坛，汇聚了行业顶尖专家和前沿技术成果。

英特尔代工技术开发高级副总裁Navid Shahriari在大会上发表了题为《AI时代的创新矩阵》的主题演讲。他表示，AI的强大潜力，既提高了人类快速、精准解决复杂问题的能力，也帮助我们开拓了视野，能够更好地理解事物与探索创新。随着数据处理需求的增长，需要在更小的芯片面积上实现更高计算能力和更低能耗。此外，并行AI工作负载的指数级增长对互连带宽密度、延迟和功耗提出了更高的要求。AI系统的扩展需求正在推动制程、封装、架构和软件领域的前沿创新。

从芯片到整个系统，英特尔正在围绕一个技术矩阵进行创新，以满足AI时代的算力需求。“从软件和系统架构到硅和先进封装，每个领域的进展都是必要的，但整个系统必须共同优化，以最大限度地提高性能和功耗，并降低成本。此外，强大的生态系统合作伙伴和新颖的设计方法论对于有效的协同优化和产品上市速度的加快也至关重要。”Shahriari在演讲中强调。

AI的成长需要技术“叠叠乐”：

本届大会英特尔一口气展示了多篇重磅研究，完整论文内容目前仅限ISSCC 2025现场参会者获取。不过别急！小编马上放送论文摘要的英文原文，带您快速解锁半导体圈前沿技术风向：

!! 硬核技术专家：按图索骥，进一步搜索原文，深度研读！

!! 科技爱好者：搭配翻译工具或AI神器使用，效果更佳！

A 0.021µm2 High-Density SRAM in Intel 18A RibbonFET Technology

with PowerVia Backside Power Delivery

Session 29 – SRAM

The accelerating pursuit of high-performance and energy-efﬁcient computing drives the re- cent breakthroughs in both semiconductor device and power delivery scheme in advanced process technology. This paper presents the industry’s ﬁrst volume silicon validated high- current 6T SRAM (HCC) and high-density 6T SRAM (HDC) designs implemented in Ribbon- FET incorporating backside power delivery with PowerVia technology over the peripheral circuits. RibbonFET transistors offer better performance per watt and improved density, and they allow ﬂexible adjustment of the effective transistor width to achieve optimal SRAM tran- sistor sizing for power, performance and VMIN. PowerVia technology features backside power routing, which enables reduced power droop and additional wiring resources on the frontside for more efﬁcient peripheral circuit design. Compared to similar designs using Fin- FET, the proposed RibbonFET SRAM design has 0.77x and 0.88x bitcell area scaling for HCC and HDC, respectively. The RibbonFET HCC SRAM demonstrated improved mea- sured VMIN without assist circuitry at 90th percentile compared to prior FinFET based de- signs that required both read and write assist circuitry. With negative bitline (NBL) write as- sist, the 34.3Mb/mm2 HDC array demonstrated 68mV better VMIN compared to the prior designs. Up to 38.1Mb/mm2 can be achieved using HDC SRAM with different array conﬁgu- ration and additional peripheral circuit compaction.

A 0.9pJ/b 108Gb/s PAM-4 VCSEL-Based Direct-Drive Optical En- gine

Session 36 – Ultra-High-Density D2D and High-Performance Optical Transceivers

This paper presents a 0.82pJ/b 108Gb/s PAM4 co-packaged VCSEL-based direct-drive opti- cal engine that integrates VCSEL driver and transimpedance ampliﬁer front end ICs, with their VCSEL and photodiode counterparts which are ﬁber terminated by direct optical wiring technology. Several circuit techniques are introduced to enable the >100Gb/s PAM4 opera- tion, including a high linearity complex-zero CTLE in the VCSEL driver and a highly linear differential TIA-FE with an active complex-zero CTLE.

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations

Session 2 – Processors

Disaggregating large systems has shown multifold advantages especially with current appli- cation trends prompting a shift towards chiplet-based architectures. To meet increasing com- puting demands, 2.5D systems should have greater interoperability between advanced tech- nology nodes from multi-Foundry, higher system memory capacity, higher I/O counts and scalable interconnect pitches. To further address the escalating memory capacity demands and mitigate memory bandwidth bottleneck prevalent in AI applications, chiplet systems should be capable of workload tailored conﬁgurations at assembly time. This adaptability enables optimal resource allocation and facilitates processing of voluminous datasets and complex AI computations.

A Fully Integrated Multi-Phase Voltage Regulator with Enhanced Light-Load-Efficiency Peak of 86%, Featuring an Autonomous Mode Transition from Hard-Switching to Soft-Switching to Discontinuous Conduction Mode in 3nm FinFET CMOS

Session 21 – Compute and USB Power

This work presents an FIVR that has an autonomous mode transition from hard-switching to soft-switching to DCM. The FIVR uses a novel high-precision, high-speed comparator that observes the low-side power switch during every switching cycle to detect negative inductor current and enable soft switching of the high-side power switch. An auxiliary detection circuit monitors the load current and changes the mode of operation to DCM where the load cur- rent is very low. One of the by-products of the transition between Continuous Conduction Mode (CCM) and DCM is the impact on the output in terms of overshoot and undershoot. Any undershoot on the FIVR output can directly impact the minimum supply voltage speciﬁ- cation of the SoCs being powered and needs to be addressed adequately. This paper also discusses DCM droop improvement techniques that use the autonomous mode transition into DCM based on load current (hitherto known as auto-DCM) and the compensation net- work to improve the DCM to CCM transition.

Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SOC Load-Current Emulator Using Low- Voltage Micron-Scale Thermal Sensors

Session 8 – Digital Techniques for System Adaptation, Power Management and Clock- ing

This paper proposes an accurate (+/-0.7°C), area-efﬁcient (20µm x 20µm), low-power (18µW), digital and low-voltage friendly (0.7-1V), current-starved ring-oscillator-based ther- mal sensor (CSRO-TS) that can be distributed across the die for ﬁne-grain thermal proﬁling of complex compute SoCs and IVR chiplets. An array of 204 sensors is implemented to demonstrate the ﬁne-grain thermal proﬁling capability that can be used to detect large tem- perature gradients (>15°C) within 100µm. An additional 12 CSRO-TS have been placed across the active area of a high-power-density package-integrated buck IVR chiplet to vali- date its resiliency in noisy environments and demonstrate its usage for thermal and reliability monitoring of the IVR power train.